An optimized majority-feedback QCA D-latch and SET/RESET-enabled SRAM cell for compact, low-latency nanoelectronic memory design

Quantum-dot cellular automata is a contender to replace the scaling of semiconductor technology as it hits physical limits of complementary metal–oxide–semiconductor technology, with its ability to switch faster, take up less space and consume less power. In this study, the design and functional verification of compact QCA data latch circuit and a memory cell suitable for SRAM operation are presented, which are designed, implemented and simulated in the QCA designer (QCAD) 2.0.3 software. The main contribution is a single-layer 14-cell D-latch with a 0.007 µm 2 footprint, reducing the layout area, latency and QCA cost compared with a similar design previously reported in the literature. Another 15-cell variant is proposed, incorporating SET and RESET control, for SRAM-type applications, reducing peak energy dissipation by approximately 22% from the 14-cell baseline. The circuits are found to be compact, low-latency circuits for next-generation nanoelectronics memory and different logic circuit design applications with reduced power dissipation. The power dissipation and polarization map of proposed circuits are implemented in QCAPro Software.