Implications of aging through HV-H3TRB on the repetitive avalanche mode ruggedness of 1.2 kV SiC MOSFETs

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have garnered significant attention owing to their superior performance. However, reliability challenges, particularly under real-world operating conditions involving multi-stress scenarios, remained to be thoroughly investigated. This study investigated the impact of high-voltage high-humidity high-temperature reverse bias (HV-H 3 TRB) on repetitive unclamped inductive switching (UIS) performance of three commercial SiC MOSFETs. The results showed that the drain source voltage ( V DS ) and stress duration under HV-H 3 TRB stress both reduced the repetitive UIS lifetime, with drain leakage current ( I DSS ) as the aging-sensitive parameter under combined stresses. The degradation was primarily driven by moisture diffusion during HV-H 3 TRB, which weakened devices' terminal, gate bus, or chip surface beneath the source bonding wires, and accelerated failure under subsequent UIS. Furthermore, a coupled lifetime degradation model describing the interaction between HV-H 3 TRB and repetitive UIS stresses was developed using V DS and stress duration as key variables. These findings provide insights into the reliability and operational lifespan of SiC MOSFETs under real-world operating conditions.