High-speed FPGA-based data acquisition architecture for pushbroom imaging sensors in LEO satellite systems

High-speed data acquisition is essential for pushbroom imaging sensors on Low Earth Orbit (LEO) satellites, where timing accuracy, word reconstruction, and frame-boundary identification affect image fidelity and real-time operation. Previous FPGA-based LVDS, SERDES, and SoC studies have mainly emphasized throughput or individual interface functions, while hardware-validated integration of independent dual-bank timing, serialized boundary detection, word reconstruction, and mission-representative line timing remains limited. This work presents and experimentally evaluates a dual-bank FPGA acquisition architecture for the NEO-1 Medium Resolution Imager. The design combines independent PLL-derived 4 × retiming clocks, serialized synchronization-pattern detection, and Serial-In-Parallel-Out reconstruction of 14-bit pixel words. Ground-based tests used the physical sensor with clock, trigger, pixel, and line-period parameters representative of the nominal 500 km imaging scenario. At a nominal 66 MHz sensor clock, the implemented acquisition period is 149,857 cycles, or approximately 2.271 ms, and the calculated aggregate payload rate is 178.282 Mbps. The non-instrumented design uses 543 logic elements, 413 registers, and two PLLs, with an estimated FPGA thermal power dissipation of 234.18 mW and positive setup and hold slack for all constrained intra-domain paths. Across five Signal Tap sessions, 138 pixel intervals yielded a mean period of 151.520 ns, with no variation resolved beyond the 3.788 ns sampling interval. One mismatch among 29,904 captured bit observations gave a capture-based bit-mismatch fraction of 3.344 × 1 0 − 5 . These results demonstrate timing-consistent and resource-efficient dual-bank acquisition under the evaluated ground conditions. Formal physical-link BER, complete-frame FER, long-duration stability, and environmental qualification remain future work.