Simulation Study of Short-Channel Effects in GAIA and GAA MOS Devices Operated in Weak-Inversion Regime Down to Deep Cryogenic Temperatures

This work investigates and compares the weak inversion behavior and drain-induced barrier lowering (DIBL) of conventional Gate-All-Around (GAA) MOSFETs and the recently proposed Gate-All-Inside-and-Around (GAIA) devices from room temperature down to deep cryogenic conditions (≈5 K). A physics-based electrostatic and transport framework is developed to analyze short-channel effects in the subthreshold regime, where cryogenic operation significantly modifies carrier statistics, threshold voltage, and subthreshold slope. Results show that while both architectures benefit from improved electrostatic control compared to planar devices, GAIA MOSFETs exhibit a systematically reduced DIBL over the entire temperature range due to an additional insulating barrier that weakens drain-to-channel electrostatic coupling. At cryogenic temperatures, DIBL is found to be primarily governed by electrostatic effects rather than thermally activated transport, remaining nearly constant over a broad temperature range before exhibiting a moderate increase below approximately 30 K. A compact analytical model is proposed, capturing the combined effects of geometry and temperature phenomena on DIBL and subthreshold conduction. The results provide new insights into the role of device architecture in mitigating short-channel effects in cryogenic CMOS technologies for quantum and ultra-low-power applications.