Cross‐Scale Integrated Photonic Convolver Based on Conjugate‐Symmetric Interference

Photonic hardware offers a promising route to high‐speed and energy‐efficient convolution computing beyond the bandwidth and power limitations of conventional electronic platforms. Here, we propose and experimentally demonstrate a cross‐scale integrated photonic convolver (CSIPC) that enables cross‐scale feature extraction through a single training process. Implemented on a hierarchically coupled finite‐impulse‐response (FIR) photonic chip, the CSIPC exploits the propagation of conjugate‐symmetric interference‐weight relations through the coupling network, together with the spatiotemporal interleaving induced by serial‐to‐parallel conversion. A single set of trained chip weights can be mapped at different output ports into a family of equivalent convolution kernels with distinct effective tap numbers and temporal intervals. By selecting the output port and tuning the input symbol rate, 2 × 4, 2 × 2, and 2 × 1 two‐dimensional convolution kernels can be realized on the same chip. We experimentally validate multifunctional cross‐scale image feature extraction and achieve a maximum single‐mode equivalent computing throughput of 0.276 TOPS. These results provide a route toward cross‐scale photonic convolution using a single device and a single training process, while improving functional integration density and enabling the reuse of trained weights and hardware resources.