Design and implementation of a wafer-level verification system targeting 2D-mesh interconnection networks

System on Wafer (SoW), as a key technological path to break through the traditional chip area limitation and achieve a leap in computing power, has become an active research focus in the field of integrated circuits in the post-Moore era. In response to the diverse, dynamic, and high-speed communication requirements in AI and high-performance computing, building a wafer-level reconfigurable switching network has emerged as an effective solution. However, constrained by implementation costs and technical barriers, current research largely remains at the stage of simulation verification using simulators such as gem5 and Garnet, lacking a verification platform that can truly reflect the physical characteristics of wafer-level system integration. To this end, this paper designs and implements a wafer-level verification system for reconfigurable switching networks, which integrates 36 switching chiplets and 288 thermal test chiplets, and provides topology/routing configuration, fault injection, and wafer-level physical parameter testing capabilities at the design level. The initial-prototype tests show that the communication rate between adjacent nodes reaches up to 145.95 Gbps and that each computing node can emulate a thermal load of up to 900 W (eight thermal test chiplets per node, each rated at up to 112.5 W).