3D NAND Scaling Performance Enhancement Using 2D MoS 2 Channel

The polysilicon channel in conventional 3D NAND flash memory shows degraded subthreshold slope and low electrostatic control over the channel upon scaling gate pitch. 3D NAND with MoS2 channel material can potentially overcome these challenges, as it shows higher mobility with a channel thickness of a few atoms. In this work, using TCAD simulations calibrated to experimental data, the MoS2material is incorporated as the channel in 3D NAND to investigate scaling performance. We demonstrate that the MoS2channel NAND performs better, even at a scaled pitch of 20nm with 10nm gate length, exhibiting a good cell current value, subthreshold slope, and improved memory performance. We investigate neighboring cell interference by analyzing the effect of barrier lowering by side transistors on the focus cell at a gate length of 10nm. This shows the MoS2channel NAND has a higher energy barrier than the polysilicon channel NAND due to better electrostatic gate control over the channel. We also demonstrate that the trapped charge during program operation is higher in MoS23D NAND at 10nm gate length, making it suitable for multi-bit operation. We analyze the retention property of the MoS2channel NAND and observe almost similar charge loss at a scaled 20nm gate pitch compared to 50nm, indicating reliable operation with gate pitch scaling. Therefore, 20 nm gate-pitch MoS2channel NAND, with a 9 V memory window, enables up to 3× higher storage density by allowing more cells to be stacked within the limited physical height of the 3D NAND stack.