Understanding and Modeling the Impact of Defects on Electrical Characteristics of Si/SiGe Heterostructures at Cryogenic temperatures

In this work, we show that the trapping in a Si/SiGe heterostructure, which is a promising platform for quantum computers, can be studied with a phenomenological approach based on employment of effective charges at channel interfaces. We consider the device as consisting of two independent channels: one in the Si quantum well and an other one in the Si capping layer. For each channel we use compact models to extract their respective parameters including the threshold voltage, gate oxide capacitance and channel mobility. By employing these parameters in our device simulator, we can model the hysteretic capacitance-voltage and current-voltage characteristics at cryogenic temperatures. Within this methodology we also extract a mobility value of both the Si quantum well and the interface channel and correlate them with defect density and barrier thickness. Next we evaluate the interface state distribution over energy Dit(E) and show that the resolved Dit(E) has a strong peak around 0.2 eV below the conduction band minimum and a peak value of 4 × 1013 cm−2 eV−1. Our Dit(E) profiles are in good agreement with those reported in literature and this supports our hypothesis that the hysteresis is driven by interface traps.