Design and security evaluation of a jitter-based 555-timer entropy source for lightweight embedded authentication

High-quality jitter-based true random number generators (TRNGs) are typically validated on FPGA or ASIC platforms, limiting their use in ultra-low-cost embedded systems. This study designs and evaluates a commodity-component entropy source comprising a free-running CMOS 555 timer, Schmitt-trigger buffer, and 12.5 ns microcontroller input-capture peripheral. A physical model maps comparator input-referred noise to per-cycle timing jitter, while a conservative entropy-crediting policy aligned with NIST SP 800–90B counts only accumulated white jitter and bounds the min-entropy of the quantized interval least significant bit. At the simulated operating point, the creditable bound exceeds 0.9999 bits per raw bit; a conservative claim of 0.5 bits per raw bit yields 0.30 kbit/s conditioned throughput and a 256-bit seed every 0.85 s. Monte Carlo experiments show that MCV and Markov estimators remain near 0.99 bits per bit even when creditable entropy falls below 0.01 bits. In contrast, the proposed windowed first-difference jitter monitor achieves 488/488 detections, no false trips, and approximately 47σ separation. Restart analysis, capture-resolution ablation, and raw-versus-conditioned statistical testing further characterize the design. The results support the 555-timer source as a low-cost seed generator, subject to device-level jitter measurement, health monitoring, and hardware validation under process, voltage, and temperature variation.