BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration

Mixed-precision quantization, which assigns precisions per-layer, per-network, per-channel, or per-parameter, is gaining traction for efficient Neural Network (NN) realization with higher throughput and lower energy. Unlike conventional fixed-precision accelerators, BF-IMNA advances the mixed-precision design space through an AP-based in-memory implementation. We present BF-IMNA, a bit fluid IMC accelerator for end-to-end Convolutional NN inference supporting static and dynamic mixed-precision without run-time reconfiguration overhead. At its heart are Associative Processors (APs), bit-serial word-parallel SIMD-like engines. We evaluate ImageNet inference with AlexNet, VGG16, and ResNet50 across SRAM and ReRAM CAM cells, mixed-precision configurations, and supply voltages. To demonstrate bit fluidity, we apply HAWQ-V3's published ResNet18 schedules to the BF-IMNA cost model and pair them with HAWQ-V3's published accuracies and model sizes. The results reveal an accuracy–Energy-Delay Product trade-off. The high-latency point is \(1.16\) points below INT8 accuracy with \(1.13×\) better EDP, while the low-latency point has \(1.91×\) better EDP and a \(45.5%\) smaller model at a \(3.00\) -point accuracy reduction. At 500-MHz, true-batch-one comparison, BitFusion provides lower absolute energy and latency, while BF-IMNA provides lower average power at all five operating points, \(2106×\) greater on-chip weight capacity ( \(32.8×\) per unit modeled area), and larger relative energy reductions at aggressive INT4 and low-latency HAWQ points.