Realisation of a Compact and Efficient Charge-Controlled Memristor Emulator for Neuromorphic Applications

The solid-state memristor developed by HP Labs confirmed the existence of the fourth fundamental circuit element and exhibited a non-linear resistance that depends on charge. However, its practical use in circuit-level applications is limited due to fabrication complexity, device variability and restricted accessibility. These limitations have spurred the development of compact, efficient memristor emulator circuits. In the present work, a novel charge-controlled memristor emulator employing two Operational Transconductance Amplifiers (OTAs), a single Voltage Differencing Transconductance Amplifier (VDTA), one grounded resistor and one capacitor is proposed. The architecture directly realises the charge-state variable via an OTA and a capacitor, yielding explicit charge-dependent memristance without requiring analogue multipliers or complex nonlinear blocks. The performance of the proposed emulator is validated through PSpice simulations in 0.18 μm CMOS technology, showing reliable operation up to 120 kHz with low power consumption. The simulation results verify the essential memristive characteristics, including pinched hysteresis loops (PHL) at the origin, frequency-dependent hysteresis reduction, non-volatility and electronically controllable resistance states. This is confirmed through both simulation and hardware implementation using the commercially available IC LM13700. The application of the proposed emulator is further demonstrated through its implementation in neuromorphic circuits, including associative learning and adaptive learning circuits.