A Compact Low Power CCII-Based LIF Neuron with Memristive Synapse Exhibiting Synaptic Plasticity

Biological neural systems perform information processing through the collective operation of neurons and synapses, in which learning is achieved by activity-dependent modification of synaptic strength. Emulating these mechanisms in electronic circuits requires compact, low-power, and scalable implementations of spiking neurons and adaptive synapses. This paper presents a compact, low-power second-generation current conveyor (CCII)- based leaky integrate-and-fire (LIF) neuron with a memristive synapse exhibiting synaptic plasticity. The proposed neuron operates in the current domain. It employs a CCII to implement weighted summation of presynaptic inputs, leaky membrane integration, and threshold-based spike generation using a low-power comparator and a PMOS-based reset mechanism. Both a resistor and a memristor are used to represent synaptic weights at the neuron inputs. At the same time, a memristive device is employed as the synapse in the learning model to provide continuously variable, emulated memristive conductance. In addition, spike timing-dependent plasticity (STDP) is implemented, in which the relative timing difference between presynaptic and postsynaptic spikes governs the change in synaptic strength. A two-neuron system comprising a presynaptic and a postsynaptic neuron, interconnected via a memristor serving as the synapse, is used to demonstrate long-term potentiation (LTP) and long-term depression (LTD). During LTP, the memristor conductance increases, whereas during LTD, the conductance decreases, thereby demonstrating synaptic plasticity similar to biological systems. The proposed circuit is designed and simulated in Cadence Virtuoso using 0.18μm CMOS technology to verify its operational performance. Simulation results validate correct LIF operation, stable learning behaviour, and low power consumption (23 μW) in standard 0.18 μm CMOS technology, confirming the suitability of the proposed neuron-synapse architecture for neuromorphic computing systems.