Classical device modelling of grain size and boundary effects on the performance of CsSnI 3 polycrystalline perovskite solar cells

In this study we systematically investigate the influence of grain size on the performance of lead-free CsSnI3 perovskite solar cells and the underlying physical mechanisms. Using a weighted-average approach, we calculate the electron and hole mobilities as functions of grain size, and develop a grain-boundary defect model based on the Matthiessen rule to establish a quantitative correlation between grain size and defect density. These extracted mobility and defect parameters are then imported into SCAPS-1D to construct a TiO2/CsSnI3/Spiro-OMeTAD planar heterojunction device, enabling a comprehensive analysis of how grain size modulates the optimization of absorber thickness, doping concentration, and interface defect tolerance. Our results show that enlarging grain size significantly enhances carrier mobility and reduces defect density, thereby effectively suppressing non-radiative recombination and improving charge extraction efficiency. The maximum power conversion efficiency (PCE) decreases from 17.82% for single-crystalline CsSnI3 to 17.75%, 17.29, 12.59, 5.06, and 0.65% for grain sizes of 100, 10, 1, 0.1, and 0.01 μm, respectively. Devices with larger grains exhibit greater tolerance to both thicker absorbers and interface defects, whereas their smaller-grain counterparts suffer from pronounced recombination losses and heightened parametric sensitivity. Notably, defects at the electron transport layer (ETL) /CsSnI3 interface are found to have a more detrimental effect on device performance than those at the CsSnI3/hole transport layer (HTL) interface. Overall, this work elucidates the intrinsic mechanisms by which grain size governs CsSnI3 device performance, providing a theoretical basis for the structural optimization of high-performance lead-free perovskite photovoltaics.