A Radiation-Hardened Self-Biased Phase-Locked Loop for Space-Grade CMOS Image Sensors

With the development of space exploration technologies, space-grade CMOS image sensors require high-performance on-chip clock circuits with low jitter, low power consumption, small area, and excellent radiation robustness. This paper presents a radiation-hardened self-biased phase-locked loop (PLL) implemented in a 55 nm CMOS process and optimized for space-grade image sensors. By replacing the conventional dual charge pump with a current adder to separate the proportional and integral paths, and incorporating a voltage-to-current converter to eliminate the loop filter resistor, the proposed design reduces the number of nodes susceptible to single-event transient (SET) effects, lowers power consumption and area, and inherently enhances radiation tolerance. Additionally, localized radiation-hardening techniques are applied to sensitive nodes to further improve SET resilience. The proposed PLL operates over a frequency range of 0.5–2.8 GHz. At an output frequency of 1 GHz, it achieves a lock time of 2.11 μs, power consumption of 3.04 mW, phase noise of −93.84 dBc/Hz at 1 MHz offset, and RMS jitter of 7.12 ps, with a core area of 0.049 mm2. Under simulated heavy-ion irradiation with a linear energy transfer (LET) of 75 MeV·cm2/mg, the hardened PLL reduces output frequency deviation by 82.86% and recovery time by 37.63% compared to an unhardened design. These results demonstrate that the proposed PLL achieves significant radiation hardness without compromising performance, power consumption, or area.