Impact of Interfacial SiO₂ Layer Thickness on the Electrical Performance of SiO₂/High-K Stacks on 4H-SiC

This study investigates the role of the electrical failure of the SiO 2 film in the breakdown of SiO 2 /ZrO 2 and SiO 2 /HfO 2 stacks. Our findings indicate that the breakdown is governed by the SiO 2 film, regardless of its thickness. This highlights the importance of carefully considering the interfacial SiO 2 layer when using high-k materials in SiC devices. We demonstrate that thicker SiO 2 layers offer several benefits, including reduced leakage, enhanced thermal stability and electrical strength, and decreased trapping. In contrast, stacks with thinner SiO 2 have a higher effective k value, exploiting the benefits of high-k dielectrics. Our experimental results suggest that a 7 nm SiO 2 layer underlying 30 nm crystalline ZrO 2 or HfO 2 provides optimal performance. Furthermore, we present calculations that reveal the trade-off between SiO 2 thickness, k value, and breakdown voltage for a 50 nm thick dielectric stack. Our results imply that a k value exceeding 20 does not yield significant benefits in 50 nm thick SiO 2 /dielectric stacks.