Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

Robustness under blocking is an important reliability metric for MOS based SiC power devices. Accelerated reverse bias (ARB) stressing, which typically employs multiple V DS stress values beyond the rated drain bias but below the avalanche voltage, is considered as the best practice for measuring the device lifetime in the blocking mode. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified modeling approach where qualification-like high temperature reverse bias (HTRB) or ARB test at a single stress voltage for a reasonable stress duration can be used to project gate oxide lifetimes under blocking.