A cryogenic 3.3-V supply, 1.6% 3σ-accuracy all-CMOS voltage reference with 58-dB PSR@10 kHz in 0.18-μm CMOS

This brief presents a cryogenic voltage reference circuit designed to operate effectively across a wide temperature range from 30 to 300 K. A key feature of the proposed design is utilizing a current subtraction technique for temperature compensation of the reference current, avoiding the deployment of bipolar transistors to reduce area and power consumption. Implemented with a 0.18- µ m CMOS process, the circuit achieves a temperature coefficient (TC) of 67.5 ppm/K, which was not achieved in previous works. The design can also attain a power supply rejection (PSR) of 58 dB at 10 kHz. Meanwhile, the average reference voltage is 1.2 V within a 1.6% 3 σ -accuracy spread. Additionally, the design is characterized by a minimal power dissipation of 1 µ W at 30 K and a compact chip area of 0.0035 mm².