Homogeneous Backside Porosification of Standard Silicon Wafers for Post-Fab Process Integration of Porous Silicon

The integration of porous silicon into standard-resistivity silicon substrates presents significant opportunities for enhancing the performance of RF devices while maintaining cost efficiency. Porous silicon, produced via electrochemical etching, offers low permittivity and high resistivity, making it a promising alternative to traditional high-resistivity silicon and trap-rich silicon-on-insulator substrates. This study addresses the challenges and solutions associated with post-fab porous silicon integration, focusing on standard-resistivity silicon substrates (10-20 Ω·cm) to avoid contamination risks and ensure compatibility with existing processes. The impact of substrate conductivity on the heterogeneity of porosification is studied, and we demonstrate that a conductive grid deposited on the wafer backside is successfully used to evenly distribute the current and assure a uniform porosification across the entire substrate, even for wafers of large diameters. This approach, validated through finite element simulations and experiments, shows promise in ensuring uniform post-fab porosification, making the technology viable for industrial-scale wafers up to 300 mm in diameter.