Technology/System Co-Optimization for FPGA Using Emerging Reconfigurable Logic Device

Reconfigurable devices are gaining increasing attention as a viable alternative and supplementary solution to the traditional CMOS technology. In this paper, we develop a more efficient field-programmable gate array (FPGA) based on the reconfigurable field-effective transistor (RFET). We use the multi-gate characteristics of RFET to redesign the key components of FPGAs, namely SRAM-controlled multiplexer and look-up tables. The compact structure of the proposed design requires fewer transistors and leads to reduced delay of the overall FPGA system. In addition, we develop a comprehensive technology/system co-design and co-optimization framework to thoroughly investigate the design space, including various device- and system-level design parameters. A series of benchmark tests show that under the optimal design, up to 32% and 13% reduction can be achieved in delay and energy-delay product (EDP), respectively, compared to the traditional CMOS FPGAs