Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200mm SiC Wafers

Electrical Wafer Sorting (EWS) on 12 000, 650 V SiC MOSFETs devices from 7 wafers of 200 mm 4H-SiC are compared with electrical deviations and defectivity of initial epitaxial layers measured using Charge biased non-Contact Voltage imaging, QUAD (Quality Uniformity And Defects), and optical surface detection with PL-imaging, respectively. We successfully demonstrate an increased prediction rate in both KR (kill-ratio) and YI (yield-impact) compared to conventional PL-imaging. It is also shown that QUAD not only supplements PL-imaging but supersedes it predicting failure in some electrical test conditions. We therefore show that the combination of QUAD and PL-imaging results significantly improves the accuracy of device failure prediction by uniquely locating faults in the wafers, and thus, improving foresight of successful device fabrication.