This design details uTCA4.0 BPM electronics for PIP-II, featuring ADCs and FPGA signal processing.
This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.
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Liu et al. (2025) studied this question.
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