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This is a Experimental Study study.

October 2, 2025Open Access

Development of BPM electronics for PIP-II at Fermilab

Key Points

The system achieves high performance with a Xilinx UltraScale+ FPGA and 250 MSPS ADCs, enabling precise measurements.
Thermal stability and signal conditioning was validated through testing, confirming robust performance metrics.
The FPGA handles complex tasks like digital down-conversion and phase drift compensation, crucial for accuracy.
Key design elements focused on effective clock management and thermal management to ensure longevity and reliability.

Abstract

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.

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