Estimation of Void Area and Position in Solder Layer of Power Semiconductor Devices Based on Temperature Distribution Characteristics

Solder layer voids have a significant impact on the thermal performance of a device, which is a key cause of the thermal failure of the device. In this paper, the area and location of solder layer voids are calculated by combining finite element modeling and experimental measurements. Specifically, by analyzing the path of heat dissipation in the device, an equivalent thermal resistance network is constructed to calculate the area and location of the solder layer voids, and the calculation results show that the increment of the path thermal resistance depends on the void area; almost independently of the location, the temperature distribution of the device changes due to the phenomenon of heat accumulation in the voids. Further, in order to calculate the position of the solder layer voids, a point thermal resistance network matrix model is proposed based on the temperature distribution characteristics of the device surface. The validity of the proposed model is verified by comparing the calculation results of the junction temperature, void area, and location with the measurement results based on experimental platforms.