Methods for Constructing High-Performance Interconnects in System-on-Chip Designs

This paper addresses the development of high-performance interconnects for System-on-Chip (SoC) designs. We outline the key requirements for interconnect implementation, emphasizing high bandwidth, low latency, and configuration flexibility. The paper proposes effective methods to achieve these requirements, ensuring optimal system performance. An experimental study is presented, investigating the impact of slave device base addresses on the performance of programs executed on embedded RISC- V cores.