Design of a low power and low noise class-C LC voltage controlled oscillator

As a key module of the phase-locked loop in the RF transceiver system, the performance of the voltage controlled oscillator directly affects the performance of the entire system. This article focuses on the application of low-power phase-locked loop systems and designs a low-power and low phase noise voltage controlled oscillator circuit. The circuit structure is improved on the C-class LC voltage controlled oscillator structure, using a resistor array and current mirror to achieve gate dynamic bias, thereby solving the startup problem of the C-class voltage controlled oscillator and ensuring that the circuit maintains the C-class working state after stable oscillation. CMOS complementary cross coupling is adopted to achieve current reuse and reduce power consumption. By removing the tail current MOSFET, the source of phase noise is reduced, making the overall phase noise of the circuit lower and more suitable for low voltage application scenarios. The design of this article is based on TSMC 40nm CMOS technology. Simulation results show that under a power supply voltage of 0.8V, the overall power consumption of the oscillator is 0.871mW. It can cover the frequency range of 2.37-2.44GHz at all process angles, and the phase noise at the 2.4GHz frequency point is less than -122.28 dBc/ Hz@1MHz Meet the performance requirements of phase-locked loops.