Hardware Implementation of Multi-LFSR Pseudo Random Number Generator

Abstract This is an implementation of a hardware pseudo-random number generator (pRNG) using multiple LFSR (Multi-LFSR) for generation, and ambient electromagnetic noise for seed generation. The pRNG algorithm is evaluated in field-programmable-gate-array (FPGA) board, which is CMOS A7. 16-bit random numbers are generated at a frequency of 50 kHz. In the FPGA setup, a new seed is set by clicking the reset button. A dedicated high speed UART is designed with a baud rate of 1,152,000 to transfer the generated numbers from the FPGA to PC.