Optimizing performance: A comprehensive study of 4-bit absolute value detector circuit using static CMOS technology

In the realm of computing advancements, the utilization of numerical comparators has become increasingly pervasive. This scholarly paper delves into the intricacies of a 4-bit absolute value detector circuit, employing a foundation rooted in static CMOS. The comprehensive exploration encompasses both circuit determination and optimization methodologies. The experimental phase entails the derivation of the simplest absolute value converter circuit through the synthesis of a logic expression derived from a truth table. Subsequently, the minimum critical path delay is computed using the path effort method. The final phase involves voltage optimization, wherein, at a voltage of 1V, the minimum critical path delay registers at 64.6, accompanied by an energy consumption of 154.2. Notably, through meticulous optimization at 0.776V, the minimum critical path delay increases to 94.2, while concurrently reducing energy consumption to 92.9. This optimization results in a 50% delay increase and an almost 40% reduction in energy consumption. The implications of this voltage optimization extend to circuits aspiring for diminished delay or consumption.