Optimization of 4-bit absolute value detector based on CMOS and PTL

This article designed and optimized a 4-bit absolute-value detector mostly using Complementary Metal Oxide Semiconductor (CMOS) static logic and transmission gate logic (PTL). In terms of overall architecture, the implementation of logic circuit functions is primarily separated into two modules, including the absolute value detector and the comparator. This paper identified the critical path of the final detector and conducted research and simplification on it to improve the general functionality of the detector which can compare the value of two numbers. To shorten the delay time in the circuit, this paper reduced the number of components on the crucial path. After calculating, the critical path delay is approximately 61.065 and the initial energy consumption for a minimum path delay is 51.06. To obtain the least amount of delay and energy use, three different techniques were used in this investigation. Ultimately, we found that the circuit optimized using the Changing V_DD and Sizing method was the most efficient. The optimized critical path delay remained around 61.065, and the energy consumption under optimized critical path delay was reduced to 10.845. The final implementation achieved a decrease of 82.2% in energy consumption while maintaining the critical path delay unchanged.