A low-latency and energy-efficient 4-bit absolute value detector for brain-machine interface applications

This research article aims to develop a 4-bit absolute value detector, balancing speed and power efficiency, with potential applications in Brain-Machine Interface (BMI) systems. The detector outputs a binary signal, indicating whether the absolute value of the input surpasses a predefined threshold. The design integrates two primary modules: an absolute value calculator and a comparator. Initially, the study focuses on enhancing the architecture of a multiplexer-based adder for absolute value calculation and selecting an efficient comparator structure, emphasizing least significant bit comparison. Further, the implementation of logic gates using Complementary Metal-Oxide-Semiconductor (CMOS) technology is elaborated. The research concludes by assessing the minimum delay achievable in the critical path, quantified at 74.22 units, and investigating strategies to minimize energy consumption. This is achieved by adjusting gate dimensions and supply voltage, aiming for a delay 1.5 times the minimum. The energy expenditure of the critical path is extrapolated to estimate the overall circuit consumption. The findings demonstrate that, at 1.5 times the minimal delay, the circuit achieves a maximum energy savings of 62.8% with a supply voltage of 0.815V.