Design and Investigation of Hetero Vertical TFET with Source Pocket for Work Function Engineering and Analog Performance Enhancement

To provide a high-efficiency device, this article presents a Vertical SiGe Tunnel Field Effect Transistor (HeteroVTFET), including and not including a source pocket. For perhaps the first time, a group IV miscible alloy SiGe is exploited in the source to improve carrier tunnelling through a source (SiGe)-channel (Si) Hetero-junction. To establish an optimal HeteroVTFET design, work function engineering and hetero-junction structure tuning are used. The simulation results carried out using the TCAD Silvaco tool are used to analyze the behaviour of developed Hetero-VTFETs. The proposed optimal structure has a higher ION/IOFF ratio (>1014), a lesser subthreshold swing (<25 mV/Dec), and a high ION current in the 10-5A/µm range.