Optimizing GaSb/Si Ferroelectric Heterojunction Vertical TFET for Low-Power Devices and Circuits

This research examines GaSb/Si-based source-pocket vertical heterojunction tunnel field-effect transistors (SP-H-V-TFET) both with and without ferroelectric oxide layers (SP-Fe-H-V-TFET), refined through Silvaco TCAD modeling for low-power electronics. The ferroelectric variant delivers a subthreshold swing (SS) of 26 mV/dec and ION/IOFF of 7.5 × 1011 at VDS = 0.5 V, markedly surpassing the baseline non-ferroelectric SP-H-V-TFET (SS: 43 mV/dec, ION/IOFF: 3.2 × 1010) with ∼1.6× steeper SS and ∼23× higher current ratio, driven by negative capacitance in the HfO2-like ferroelectric film. The GaSb source boosts band-to-band tunneling at the type-II heterojunction, complemented by source-pocket optimization for enhanced electrostatics. Analyses of temperature sensitivity, analog/RF figures-of-merit, and circuit-level transient/DC responses validate the ferroelectric design’s excellence in stability, speed, and efficiency, establishing its potential for advanced ultra-low-power systems.