Advanced packages for high-end applications require higher bandwidth and larger number of I/O signal processing. To achieve the highly demanded performance, heterogeneous integration has been proposed as the technology to integrate different functional chips into a single package system, while the Moore's law is approaching its limit. For example, logic devices integrated with high bandwidth memories in fine pitch has been already commercialized. In order to integrate sophisticated multiple chip, the size of Si interposer and substrate are getting larger. However, an increase of the package size causes various challenges such as warpage control of the package and maintaining package level reliability.We have previously reported the assembly process and reliability of the large size (100 mm x 100 mm) 2.5D package test vehicle [1]. In this work, the size enhanced 2.5D package with 120 mm x 120 mm substrate was designed and fabricated. To reduce the warpage, we adopted the molding procedure, which was the combination of capillary underfill (CUF) and over molding instead of a batch compression molding with liquid compression mold underfill (LCMUF). In addition, it was demonstrated that the stiffener played a crucial role. We examined the effect of its material and footprint. As a result, the stiffener made of SUS430 and width of 28 mm in a longitudinal direction and 30 mm in a lateral direction was chosen as an appropriate one.After assembly of the 2.5D test vehicle, thermal reliability test was carried out. The fabricated package passed the 1000-cycle thermal cycle test.
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Hirano et al. (2024) studied this question.
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