Current Temperature Stress Induced Threshold Degradation on Corbino a-InGaZnO Transistors

This is the authors' abstract. We don't add key points for this paper.

Although Corbino a-InGaZnO (IGZO) based thin-film transistors (C-TFTs) featuring self-heating mitigation show a great potential in display applications, degradation effects induced by coupling of self-heating and bias temperature instability on C-TFTs are observed under the current temperature stress (CTS), and the hot-spot in the IGZO channel would aggravate threshold-voltage shift. To address and optimize the issue, the a-IGZO-based TFTs are fabricated and the current-temperature instability (CTI) is systematically investigated with the temperature ranging from room temperature to 60 °C. An empirical model is provided to fit and analyze experimental results. Notably, the asymmetry effect is clearly observed in C-TFTs, where an outer ring electrode as drain-side shows a superior performance due to the dispersive electric field distribution. To further comprehend trade-offs of CTI and current density, the technology computer-aided design (TCAD) simulations are employed to investigate effects of voltage scaling and gate-to-source/drain offset. These results will boost the design technology co-optimization flow for future large-scale circuits with scalable and stable Corbino TFTs.