A Low-Power 23.5-to-28.8 GHz CMOS Oscillator with Flicker Noise Up-Conversion Suppression Using Drain Current Shaping Technique

This paper presents a low-power complementary CMOS mm-wave Voltage-Controlled Oscillator (VCO) with a new flicker phase noise (PN) reduction technique based on the impulse sensitivity function (ISF). Drain current-shaping technique is introduced in voltage-biased oscillator to suppress the up-converted flicker noise of its cross-coupled pairs of active devices. Drain current waveform is effectively shaped to exhibit its minimum levels at the VCO differential output zero crossings where the VCO is most sensitive to noise (maximum ISF values), while featuring its maximums at the VCO least sensitive intervals (minimum ISF values). To validate the proposed flicker PN reduction approach, a 23.42-to-28.88 GHz current-reuse VCO is designed in standard 65 nm RF CMOS technology. The proposed technique achieves a flicker PN reduction by more than 24 dBc/Hz at 1 kHz offset as opposed to the conventional design. The designed VCO features an ultra-low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/f³</tex> PN corner of 400 Hz, while consuming power of no more than 1.2 mW using a 1 V supply. Moreover, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/f²</tex> PN results show levels of −105.7 and −125.7 dBc/Hz at 1 and 10 MHz frequency offsets, respectively. Consequently, the designed oscillator achieves a peak figure-of-merit (FoM) of 194 dBc/Hz and 200.34 dBc/Hz FoMT at 1 MHz offset with a 20.76 % tuning range.