Design of Spin-FET Electrical Model for Basic Gates

In conventional CMOS technology, the spin transistor (Spin-FET) is the most promising technology for resolving power consumption, speed, and non-volatility problems. This paper briefly explains the Single Gate Spin-FET electrical model for InAs channel material with a channel length of 800 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> m, which is suitable for performing digital logic functions for the local geometry of Spin-FET. Also, the simulation results were validated by performing their transient and DC simulation for different channel lengths and various spin polarization rates of the tunnel junctions. However, an inverter and a buffer gate are built using complementary Spin-FETs in order to confirm the functionality of the local geometry model. This allows for a replication of the inverter and buffer gate's behavior.