Simulation study demonstrates improved analog and RF performance in tri-metal gate FinFETs, suggesting viable utility for ultra-low-power VLSI design.
In this manuscript, a 3D simulation model of FinFET is proposed. The device is designed in such a manner that the gate is made with three metals of different work functions, so it’s named as Tri-Metal Gate (TMG) FinFET. The work function at source/channel junction is kept high in comparison to the drain/channel junction to reduce DIBL and improve transconductance. This structure improves ONstate current, with suppressed OFF-state current. Further DC and analog/RF characteristics such as transfer characteristics, parasitic capacitance (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</inf> , C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</inf> ), transconductance (g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> ), cut off frequency (f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ), output transconductance (g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> ), transconductance generation factor(TGF) are investigated. A comparative analysis of the proposed device with an existing device is also performed and results are studies. Above parameters support its utility at ultra-low power VLSI. The device has been simulated using TCAD simulator.
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Saraswat et al. (2020) studied this question.
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