Design and temperature assessment of analog/RF and linearity parameters on dual material gate junctionless FinFET at 7 nm technology node for nano scale applications

The dual-material gate junctionless FinFET (DMG JLFinFET) has emerged as a promising device in semiconductor technology due to its enhanced capability to suppress short-channel effects (SCEs). This work presents a comprehensive study on how temperature variations affect the electrical behavior of DMG JLFinFETs, particularly for devices scaled to the 7 nm technology node. Essential DC parameters—such as subthreshold swing (SS), drain-induced barrier lowering (DIBL), and the I ON /I OFF ratio—were evaluated over a temperature span of 200 to 400 K. In addition, the study examines how temperature impacts key analog and radio frequency (RF) parameters, including gate-to-drain capacitance (C gd ), gate-to-source capacitance (C gs ), total gate capacitance (C gg ), transconductance (g m ), cutoff frequency (f t ), transconductance generation factor (TGF), intrinsic delay (τ), gain-bandwidth product (GBW), and transconductance frequency product (TFP). The investigation also addresses how thermal conditions influence linearity performance, focusing on metrics such as second-order transconductance (g m2 ), third-order transconductance (g m3 ), voltage intercept points (VIP2, VIP3), third-order input intercept point (IIP3), and the 1 dB compression point. The findings of this investigation demonstrate that the DMG JLFinFET exhibits promising electrical, analog, and RF performance characteristics, making it a viable candidate for advanced communication applications.