Compact Dual-Core Drive Stage Using Three-Winding Transformer for CMOS Broadband Power Amplifier

We present a novel broadband power amplifier (PA) architecture designed to achieve both high output power and a compact chip size in CMOS. This architecture features a dual-core drive stage and a compact vertical three-winding transformer (TF). Implemented using a 65-nm bulk CMOS process, precise measurements validate its feasibility. The measured 3-dB bandwidth (BW <tex-math notation="LaTeX">3 dB</tex-math> ) of the proposed PA is 8 GHz (7–15 GHz), with a fractional BW (FBW) of 73%. In the 10–15-GHz range, it demonstrates 19–22-dB gain, 22–23.2-dBm <tex-math notation="LaTeX">PSAT</tex-math> , and 30 <tex-math notation="LaTeX">$%$</tex-math> –41.5% PAE (all under the same bias conditions). During testing at 10–15 GHz (FBW: 40%) with a 1-CC 64-QAM OFDM signal (all under the same bias conditions), the PA demonstrates an average output power of 15.6–17.1 dBm and an average efficiency of 11.8 <tex-math notation="LaTeX">$%$</tex-math> –18.4% at <tex-math notation="LaTeX">$-$</tex-math> 25-dB error vector magnitude (EVM) <tex-math notation="LaTeX">ᵣₘₛ</tex-math> .