A D-Band Power Amplifier With 60-GHz Large-Signal Bandwidth and 7.6% Peak PAE in 28-nm CMOS

This letter presents a <tex-math notation="LaTeX">D</tex-math> -band four-stage differential common-source (CS) power amplifier (PA) in 28-nm bulk CMOS. To expand the large-signal bandwidth and improve the efficiency of the PA, transistor size and layout of the CS stage have been optimized. Neutralizing capacitor is utilized to boost the gain and improve the stability of the CS stage. Additionally, transformer-based matching networks are introduced to realize the wideband output match and multistage staggering scheme, thereby expanding the bandwidth of the PA. The proposed PA achieves a 38-GHz (114–152 GHz) large-signal 1-dB bandwidth and a 60-GHz (110–170 GHz) large-signal 3-dB bandwidth. The measured maximum Psat and OP <tex-math notation="LaTeX">1~dB</tex-math> are 9.5 and 4.2 dBm with a peak power added efficiency (PAE) of 7.6% at 124 GHz. The measured peak S <tex-math notation="LaTeX">₂₁</tex-math> is 21.9 dB at 160 GHz. To the best of our knowledge, the proposed PA demonstrates the broadest large-signal bandwidth among <tex-math notation="LaTeX">D</tex-math> -band PAs fabricated in CMOS technology.