Modeling and Demonstration for Multi-level Weight Conductance in Computational FeFET Memory Cell

With the advance of artificial intelligent (AI), analog computation-in-memory (A-CiM) has been extensively studied for edge-AI applications, due to their low power operations. In this study, we demonstrated the modulation of multi-level weight conductance of ferroelectric field-effect-transistor (FeFET) devices as a synaptic cell. For the precise conductance modulation of FeFET synapses, we developed the simulation framework by combining a ferroelectric switching model, FeFET threshold (Vth) model, and accurate MOSFET drain current model. Then, the poly-Si channel FeFET synapses confirmed the multi-level conductance states (≥ 16-level/cell) with ultra-low current levels and stable retention, which improves energy efficiency of inference for image classification.