Asynchronous Continuous Time Pipeline Analog-to-Digital Converter

Continuous time systems offer a number of advantages over conventional digital signal processing. Conventional digital signal processing is limited by quantization error, frequency aliasing, and discrete time lag. Continuous time systems have no inherent quantization error, are free of frequency aliasing, free from discrete time lag, and provide a form of compressive sensing. For a 4-bit equivalent analog-digital-converter (ADC), Vezyrtzis and Tsividis demonstrated offline reconstruction of a continuous time signal with > 100 dB signal-to-noise-and-distortion (SINAD) ratio. Conventional Shannon sampling pipeline analog-to-digital converters are limited by (1) aperture jitter (sample timing jitter) (2) overlapping pipeline stage voltage levels, (3) multiple voltage reference stages, (4) multiple bit changes in multiple pipeline stages, and (5) complex amplitude and timing error correction. Conventional pipeline analog-to-digital converters are not designed to guarantee only one state change occurs a time. A patent pending continuous time pipeline analog-to-digital converter is presented that overcomes many of the limitations present in conventional analog-to-digital converters. A continuous time ADC is not based on Shannon sampling, and it does not have the extremely low aperture jitter requirements found in conventional GHz speed ADCs. Continuous time pipeline analog-to-digital converters can potentially achieve 10 plus equivalent number of bits (ENOB) at greater than 10 GHz speeds.