An Area Efficient Low Current Mismatch Charge Pump with Loop Filter for PLL Applications

This research focuses on the development of a charge pump with enhanced performance in terms of low current mismatch and area efficiency, utilizing 90nm CMOS technology. Unlike traditional charge pumps that may exhibit non-linearity effects, this paper introduced casco de technology using M OS-FETs as an alternative to diodes and op-amps. This not only occupies a very small area and reduces power consumption but also minimizes current mismatches. The efficiency of the proposed charge pump is also evaluated through process corner and temperature swept analysis. The designed charge pump occupies a compact area of only 153.95 /Lm 2 and consumes 117.8 /LW of DC power. Notably, between 1.04V and 1.44V, no current mismatch is observed. Our designed charge pump surpasses the current industry standard across various parameters including active layout area and DC power consumption offering improved performance in PLL Applications.