Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process

This paper proposes standard cell layout style and transistor reordering algorithm to reduce the area penalty in the double-diffusion break FinFET process. First generation of FinFET process technology requires a double-diffusion break to shutdown leakage current under the dummy gate. Double-diffusion break at the edge of the standard cell requires two additional unit cell for the dummy gates. The proposed layout structure shares the common potential nodes to reduce the use of double diffusion break. Transistors in a standard cell have diffusions with same potentials. These same potential nodes can be placed adjacent or overlapping if the electrical performance meets the requirement. We propose a FinFET cell layout style which source nodes can be shared with adjacent cells. We also propose a transistor reorder algorithm to improve the use of common potential node sharing. Experimental result show that the proposed cell library with new layout style and reordering algorithm achieves 4.40% area reduction in average.