A 919GMACs/J Reconfigurable SIMD Array Processor for Baseband Signal Processing

As the next-generation mobile communication standards combine AI/ML features, it is critical to improve flexibility for hardware implementation with sufficient efficiency and minimized latency. Coarse-grained reconfigurable domain-specific processors perform well in the trade-off between flexibility and efficiency. The efficiency can be further increased by processing data in a vector-matrix way. This paper presents a reconfigurable single-instruction multiple-data (SIMD) array processor with high flexibility and efficiency for baseband signal processing with AI/ML operations. The proposed SIMD array processor reaches high efficiency by maximizing hardware utilization for the supported operations. Hardware utilization is increased by efficient scheduling and data interleaving. Matrix multiplication can be accelerated by parallel processing. Full hardware utilization can be achieved through the output-stationary dataflow. Designed in a 16-nm CMOS technology, the proposed processor integrates 4.3M gates in core area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.78mm²</tex> . It dissipates 223-to-353mW at a frequency of 200MHz from a 0.9V supply, achieving peak energy efficiency of 919GMACs/J. Compared to the state-of-the-art reconfigurable domain-specific processors with similar flexibility, this work achieves 3.1-to-12.9× higher energy efficiency.