Co-Design of a Low-Power RISC-V Processor and a Reconfigurable Neural Network Accelerator for Edge AI Computing

The operational efficiency of the compact edge AI accelerator is susceptible to variations in network structure and data transmission speed. To address this issue, this study proposes a collaborative design scheme for digital integrated circuits. By adjusting the working mode of the computing array and coordinating with storage and power management, the operational efficiency of the accelerator is improved. The research tested three network models trained on the publicly available Digits dataset. The results showed that the average accuracy of integer reasoning ranged from 96.78% to 97.33%, and the average loss was at most 0.11 percentage points compared to floating-point reasoning. In a cost model with 64 processing units and 8 KiB memory, compared to a fixed array, this scheme reduced the inference delay by 14.83% to 18.74%, decreased the single-inference energy consumption by 6.86% to 8.81%, and increased the area by 7.58%. Further experiments demonstrated that reducing the waiting time between data transmission and computation plays a major role in improving operational efficiency. Allowing the computing array to flexibly adjust its working mode can also increase the utilization rate of processing units, but this improvement is still limited by data transmission capabilities. In the hardware resource allocation test, the scheme with 64 computing elements and 1 KB memory further reduced the area while keeping the power consumption basically unchanged. These results indicate that this design can balance operational efficiency and hardware overhead to a certain extent, but the specific effect still needs to be verified through actual hardware testing.