A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain

The voltage droop, caused by rapid current fluctuations in high-performance microprocessors, leads to critical functional failure due to timing violations. A common solution is adding a supply voltage guardband, but it incurs a significant power overhead. Alternatively, we may slow down the system clock temporarily to avoid timing violations when the droop occurs (Fig. 1, top). Recent studies have suggested various high-speed droop detection and mitigation techniques [1–6]. Previous analog-oriented approaches are cumbersome to integrate into a microprocessor due to the large area [1–3] and the need for a dedicated supply [1], [3]. On the other hand, digital approaches allow for easier integration, sharing the supply with logic and occupying a small area [4–6]. However, they provide limited clock stretch ranges [4], [6] or are susceptible to supply voltage fluctuations due to abrupt frequency change when returning to normal operation after mitigation [4], [5].