14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS

Drastic workload variations in multicore processors [1] inherently cause severe dynamic voltage droops, including sharp 1 st -order droops of around 100mV/10ns and frequent periodic droops when executing instructions using multiple cores [2–6] (Fig. 14.2.1 [top]). Several on-chip voltage sensors have been designed, but they suffer from several cycles of latency between workload activity changes and the detection of droop event. Some proactive designs were proposed to predict the future power at or even before a droop occurs [4–6], such as APOLLO by using key signals' toggling-based power estimation [6]. However, droop is not only determined by load current variations, but also affected by the present voltage, as well as the power delivery network (PDN) determined by package inductance, on-chip and board decoupling capacitance and resistance. Therefore, previous proactive approaches face challenges of prediction accuracy and lack proper droop mitigation strategies.