ISSCC 2024 Session 14 Overview: Digital Techniques for System Adaptation, Power Management and Clocking

In Paper 14.2, Southeast University, Nanjing, describes a 28nm CMOS proactive voltage droop mitigation approach with ML-based current prediction, dual-PD control-based voltage prediction, and a physical power delivery network model, which results in 0-latency and a small performance loss of only 0.6% when applied to an 8-core processor.