Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications

In this work, impact of cryogenic operation temperatures on latchup in 28nm planar bulk CMOS technology is discussed for quantum computing applications. Measurement and simulation results indicate that at low temperatures the sheet well resistances experiences 60% increase. Further simulations reveal that the vertical resistance increases leading to latchup risk. However, the current gain product of the parasitic bipolar transistors reduces, and holing voltage is increased with low temperatures which can compensate the latchup risk.