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3-dimensional chiplet device architectures are expected to provide improved device performance, efficiency, and footprint beyond what is capable with 2-dimensional scaling technologies. Thick resist lithography of damascene and plating resists, as well as organic dielectric materials, plays a critical role in chiplet integration. However, thick resist lithography requires viscous resist solutions, specialized tooling, and long processing times. This makes patterning using these resists inherently prone to uniformity issues, which has become a crucial issue for scaling. This work highlights two strategic areas of thick resist patterning development: improved resist coating methods; and enhanced focus control during exposure. Herein, we show a track-based method for carefully controlled uniformity of the resist coating thickness, with some sacrifice of through-put. In addition, we show stepper-based focus methods to account for die level variations in resist and wafer thickness, as well as local topography. Combined, these provide precise cross-wafer control of thick resist dimensions.
Bottoms et al. (Wed,) studied this question.