Design and Analysis of Low Power Security-Oriented SRAMs

The vulnerability of security systems to Power Analysis (PA) attacks, exploiting the analysis of current from the system's power supply, poses a serious threat. Embedded memories, a critical component of these systems, often utilize 6T Static Random Access Memory (SRAM) cells. However, Side-channel PA attacks can be launched against common SRAM cells because of the intrinsic connection between the written data and current characteristics. In our prior work, we introduced a security-focused 7T SRAM cell [1], incorporating an additional transistor and a two-phase write operation to significantly mitigate the relation between power consumption and stored data while write operations, providing resistance against such attacks. In this paper, we present a security-oriented 8T SRAM [8] that leverages a sleep transistor to reduce the power consumed by the security-oriented 7T SRAM. Additionally, we introduce a 10T SRAM that fulfills the functionalities of the security-focused 8T SRAM, offering benefits such as faster access times, improved stability, and reduced leakage current. Implemented in a 90 nm technology, the proposed SRAM cells exhibit approximately 250% lower Static Power Dissipation compared to the original security-oriented 7T SRAM [1].